The present invention is related to provide a central processing unit having a fixed length instruction for varying memory addresses, offsets and immediate data.
As it is apparent from FIG. 5, a conventional central processing unit comprises a register file 7, including a GPR (General Purpose Register) configured to be suitable to an architecture that is a region to ease the access of a user and a SPR (Special Purpose Register) used for a special purpose; an instruction register 4 for latching an instruction patched from a memory; a decode/control portion 5 for decoding an OP code and an operand latched in the instruction register 4 and producing a predetermined control signal according to an instruction; a operating portion 6 for processing the instruction decoded in the decode/control portion 5; a memory data register 1 for latching/buffering data when writing data in the memory or reading data from the memory; a memory address register 2 for latching/outputting an address counted in a program counter; and a control signal register 3 for buffering a control signal input from an outside source.
The instruction of the central processing unit called xe2x80x9cMachine Languagexe2x80x9d, comprises an OP code which is expressed in an arrangement of binary bits and represents operation, and an operand which is subject to be operated by the OP code.
Seeing an ADD instruction as an example for OP codes and operands, xe2x80x98A=B+Cxe2x80x99 is to add xe2x80x98Bxe2x80x99 and xe2x80x98Cxe2x80x99 to each other and store its result at xe2x80x98Axe2x80x99. Herein, xe2x80x98+xe2x80x99 is an OP code for representing the operation, and xe2x80x98Axe2x80x99, xe2x80x98Bxe2x80x99 and xe2x80x98Cxe2x80x99 are operands as objects to be operated upon. The above expression may be, xe2x80x980001 0000 0001 0010xe2x80x99 if represented in a machine language, in which xe2x80x980001xe2x80x99 is an OP code that symbolizes xe2x80x98+xe2x80x99 xe2x80x980000xe2x80x99, xe2x80x980001xe2x80x99 and xe2x80x980010xe2x80x99 are operands that A, B and C are symbolized. The representation of the binary digit may be often embodied as a hexadecimal digit because reading is difficult. The representation of the hexadecimal digit in the above example becomes xe2x80x980xc3x971012xe2x80x99. In the machine language, the operand includes a register, a memory address, an offset and immediate data.
The number of the registers is limited to 32 in many cases. For example, if the number of registers is 16, it can be represented as an operand of 4 bits (2**4=16). But, in case of a memory address, a 32-bit central processing unit can use a memory of 4 G bytes. It needs a 32-bit address for its representation. Therefore, the operand length defining it becomes longer. In case of the offset and the immediate data, the operand length becomes longer similar to the case of the memory. If the operand length becomes longer, the length of the machine language gets longer. If the length of the machine language becomes longer, the program size is increased and the efficiency becomes bad.
Because of these reasons, each of the central processing units should have a technical method for representing the operand, efficiently. 80386 used in IBM-PC has a Multi-Byte Length Instruction. For example, the instruction machine language xe2x80x98MOVExe2x80x99 of 80386 is defined based on the operand length as follows:
Also, MC68000 has a Multi 16-bit Length Instruction similar to 80386. The variable Length Instruction, as described above, has an advantage of being able to represent any length of an operand, but has disadvantages in that it is difficult to process the instruction decoding and the exceptional situation, etc., because the length of the machine language is changed. The central processing unit having the variable length instruction is called CISC (Complex Instruction Set Computer).
On the other hand, in RISC (Reduced Instruction Set Computer) the length of the machine language is fixed. Given one example, MIPS-R3000, SPARC, ARM-7, etc. has a 32-bit fixed length instruction, SH-3 manufactured by Hitachi Co. has a 16-bit fixed length instruction. These fixed length instructions ease the instruction decoding, the exception process and the adoption of a pipe line to realize the high performance of the central processing unit because of the constant length of the machine language. On the contrary, it accompanies the restriction to the operand length because the instruction length is fixed.
For example, MIPS-R3000 has a memory of a 32-bit capacity. Nevertheless, an offset capable of representing in a machine language is a 16-bit and is a 32-bit central processing unit but the length of an immediate constant is limited to 16-bit. Thus, it becomes one of the reasons the program coding is difficult and its performance is deteriorating.
Also, an instruction, xe2x80x98MOVExe2x80x99, is an operation for copying the content of one register to another register, in which the register operand has a 5-bit length because MIPS-R3000 has 32 registers. Assuming that the OP code for representing xe2x80x98MOVExe2x80x99 is defined into a 6-bit, the fixed length instruction can be defined into 16-bit instruction. But, in order to use the fixed length instruction, 16-bit representable instruction is represented as a 32-bit one. But, the 32-bit fixed length instruction has disadvantages that the operand length is limited and has an unnecessary lengthy instruction.
Consider another example of TR-4101, TR-4101 has a 16-bit fixed length instruction and the function of extending a part of the fixed length instruction and the operand. For example, an instruction xe2x80x98LOADxe2x80x99 forcing data to be fetched from a memory includes an OP code for representing xe2x80x98LOADxe2x80x99 and a target register representing a register fetched and stored, an index register indicating the positions of an operand and a memory and an offset operand representing the offset from the operand and index. In order to represent these OP codes and various kind of operands on a 16-bit length instruction, TR-4101 limits the offset to a 5-bit. But, the 5-bit offset is not enough to represent the memory position. So, TR-4101 uses an instruction, xe2x80x98EXTENDxe2x80x99.
The instruction, xe2x80x98EXTENDxe2x80x99, includes an OP code of 5 bits and an immediate constant operand of 11 bits. Herein, the 11-bit immediate constant operand is interpreted according to the instruction positioned next to the instruction xe2x80x98EXTENDxe2x80x99. For example, when the xe2x80x98LOADxe2x80x99 next to the instruction xe2x80x98EXTENDxe2x80x99 appears, the 11-bit immediate constant operand of the instruction xe2x80x98EXTENDxe2x80x99 and a 5-bit offset of the instruction xe2x80x98LOADxe2x80x99 concatenated each other to represent the 16-bit offset.
The instruction extension technology of TR-4101 is only to extend the offset and the immediate constant into a 16-bit and does not resolve the limitation of the operand length that the conventional RISC central processing unit has. The operand extendable instruction makes the pointing-out of the operand different according to the existence of the instruction xe2x80x98EXTENDxe2x80x99. The instruction that the preceded instruction xe2x80x98EXTENDxe2x80x99 is concatenated is taken into one instruction. In other words, it has disadvantages that the exception process next to the instruction xe2x80x98EXTENDxe2x80x99 cannot be operated and the request in response to the peripheral apparatus cannot be processed in a real time.
Accordingly, in order to resolve these disadvantages and problems, an object of the invention is to provide a central processing unit having an extension instruction which takes advantages from a CISC and a RISC to represent all length of memory addresses and offsets and immediate data, to simplify an instruction decoder circuit using a fixed instruction as well as to facilitate the exception process, so that a pipe line and a MMU (Memory Management Unit) are simplified.
Another object of the present invention is to provide a central processing unit having an extension instruction to be able to return to the next routine which the process of extension instruction which the process of extension instruction is stopped after performing immediately an exception process procedure even though an exceptional situation next to the extension instruction happens.
In order to accomplish these objects, a central processing unit having an extension instruction, including a register file, the collection of registers that is a small scale of the memory unit in which the access speed is fast; an inner bus connected to the register file to transfer/receive information; an outer bus buffer connected to the inner bus to connect an outer bus thereto; a function block connected to the inner bus and for executing the calculation function; an instruction register connected to the inner bus and for memorizing the instruction in the procedure of being executed; a control block connected to the instruction register and for interpreting the instruction and generating/outputting a control signal to the register file, the inner bus, the outer bus buffer, the function block and the instruction register; and one or a plurality of status flags for representing a calculation resulting status of the function block, a status of the instruction register, a status of the control block, in which the register file includes one or a plurality of accessible general registers for storing calculation source data and calculation resulting in and memorizing memory addresses, one or a plurality of special registers for memorizing information necessary to the operation of the central processing unit, and one or a plurality of inner registers for memorizing special functions necessary for the operation of the central processing unit at a register that the programmer is not accessible, the calculation interim procedures, etc.; the status flag includes ones that a programer is accessible or not accessible to and a program counter for memorizing the memory address that the program proceeded by one special register is stored; the program address that the program counter points out is output to the inner bus; the program address output to the inner bus is output through the outer bus buffer to the outer memory address memorizing the program; the instruction is read from the outer memory pointed out in the described method and transferred through the outer bus buffer to the inner bus; the instruction is stored in the instruction register that is one of the inner registers, interpreted in the control block to generate the control signal, to execute the instruction and change a related status flag, in which the instruction stored in the instruction register and interpreted in the control block includes only the OP code for representing the operation or the OP codes and an operand field having one or a plurality of operands subjected to be operated with respect to the system operation; the OP code and the operand include one or a plurality of binary bits, in which the operand is interpreted/executed into an address operand representing the memory address, an offset operand representing the offset from the memory address memorized in the general register or the special register, an immediate constant operand representing an immediate constant for use in the calculation or the memory address or the control, or a register operand representing the register, etc., furthermore comprising: an extension register having only an extension data field, or an extension register having the extension data field as one element for memorizing extension data in an accessible register, in which the instruction, including the OP code for representing the operation of memorizing the extension data in the extension data field of the extension register and the immediate constant operand, is interpreted in the control block to memorize the immediate constant operand in the extension data field of the extension register, the extension instruction including the OP code and the operand field concatenates the operand field included in the extension instruction in the control block to the extension data memorized in the extension data field of the extension register in order to form a new operand field and is interpreted into/executed instruction having a newly formed operand field.
Also, the modified instruction including an OP code and an operand field concatenates extension data memorized in the extension data field of the extension register to the operand field included in the modified instruction to form a new instruction, so that the newly formed instruction can be interpreted and executed.
Also, according to the invention, the central processing unit having an extension instruction furthermore comprises an extension flag for representing the status of the extension data field of the extension register, which is one of the status flags, including one or a plurality of bits that a programmer has an access, in which the instruction including the OP code for representing the operation of memorizing the extension data in the extension data field of the extension register and the immediate constant operand is interpreted in the control block to memorize the immediate constant operand in the extension data field of the extension register and executed in the control block to change the status of the extension flag; the extensible instruction including the OP code and the operand field is interpreted into/executed instruction having only the operand field included in the extensible instruction in the control block according to the extension flag status, or concatenates the operand field included in the extensible instruction to the extension data memorized in the extension data field of the extension register to form a new operand field and is interpreted into instruction having a newly formed operand field which is executed to execute the extensible instruction in the control block and change the extension flag status.
The invention comprises a central processing unit including an extension register ER, means for representing the status of the extension register, an instruction for storing a value in the ER and an instruction for forcing the operand interpretation to be based differently on the status of the extension register. The invention can realize a central processing unit having a fixed length instruction and for varying the lengths of a memory address, the offset and an immediate constant.